/********************
    Author: Chen Xinke
    Function: Test memory read and write errors
    Usage: include this file in the start.S, after initialize cache and before copy Pmon Text to the memory;
           put the function at the end of this file--hexserial64_1-- in the code segment in start.S.
    Note: the macro TEST_BASE and PATTERN_BASE may need to be changed according to the address space.
********************/
//change the MEMSIZE here
#define MEMSIZE_1G

#ifdef  MEMSIZE_1G
#define PATTERN_BASE   0x9800000090000000
#define TEST_BASE   0x9800000090100000
#define UNCACHED_TEST_BASE   0x9000000090100000
//#define TEST_LIMIT  TEST_BASE + msize
#else
#ifdef  MEMSIZE_2G
#define PATTERN_BASE   0x9800000080000000
#define TEST_BASE   0x9800000080100000
#define UNCACHED_TEST_BASE   0x9000000080100000
#else
#ifdef  MEMSIZE_4G
#define PATTERN_BASE   0x9800000100000000
#define TEST_BASE   0x9800000100100000
#define UNCACHED_TEST_BASE   0x9000000100100000
#else
//MEMSIZE_512M
#define PATTERN_BASE   0x9800000020000000
#define TEST_BASE   0x9800000020100000
#define UNCACHED_TEST_BASE   0x9000000020100000
#endif
#endif
#endif
	TTYDBG("\r\nStart Debuging Memory Test...\r\n")
	TTYDBG("Address Stuck Testing...\r\n")
//debug fatal errors
//write memory
    //use uncached address space here
    dli     t8, 64  //max print errors 64
	dli 	t1, UNCACHED_TEST_BASE
    dli     t3, 128  //loop counter
1:	
    sd      t1, 0x0(t1)
    nop
    daddiu  t1, t1, 0x8
    daddiu  t3, t3, -1
    bnez 	t3, 1b
	nop
	TTYDBG("write done...\r\n")
//read memory and compare
	dli 	t1, UNCACHED_TEST_BASE
    dli     t3, 128  //loop counter
1:
    ld	    t4, 0x0(t1)
    move    t0, t1
    beq     t4, t0, 2f
    nop
    //error detected!!! print address, expected data and read data
    bal     hexserial64_1
    nop
    daddiu  t8, t8, -1
    bltz    t8, 21f  //detect enough errors, go to test end
    nop
2:
    daddiu  t1, t1, 0x8
    daddiu  t3, t3, -1
    bnez 	t3, 1b
	nop
	TTYDBG	("Stuck Testing done!\r\n")
/***************
use register: t0~t9, a0~a3, v0~v1
t0: test pattern content
t1: current address
t6: test pattern base
t2: address interval
t3: max address
t4,t5: volatile
t7: volatile
t8: error counter---used to control the max detected error number
t9: loop control
    bit[3:0]: data pattern
    bit[7:4]: address pattern
**************/
//data patterns(8 bytes)
/**************
pattern: 
OneZero      0x0000000000000000 0xffffffffffffffff
JustZero     0x00000000
JustOne      0xffffffff
FiveA8       0x5aa5a55a5aa5a55a 0xa55a5aa5a55a5aa5
WalkOnes     0x01010101 0x02020202 0x04040404 0x08080808 0x10 0x20 0x40 0x80
WalkInvOnes  0x01010101 ~  0x02020202 ~ 0x04040404 ~ 0x08080808
WalkZeros    0xfefefefe 0xfdfdfdfd 0xfbfbfbfb 0xf7f7f7f7 0xef 0xdf 0xbf 0x7f
JustA        0xaaaaaaaa
JustFive     0x55555555
ZeroOne      0x00000000ffffffff
****************/
//address generator(address interval)
/********
* pattern 0: 8
* pattern 1: 8K(SDRAM page size 1KB)
* pattern 2: 16K(SDRAM page size 2KB)
*********/
#define PATTERN_1_0 0xb5b5b5b5b5b5b5b5
#define PATTERN_1_1 0x4a4a4a4a4a4a4a4a
#define PATTERN_2_0 0x5aa5a55a5aa5a55a
#define PATTERN_2_1 0xa55a5aa5a55a5aa5
#define PATTERN_3_0 0x0101010101010101
#define PATTERN_3_1 0x0202020202020202
#define PATTERN_3_2 0x0404040404040404
#define PATTERN_3_3 0x0808080808080808
#define PATTERN_3_4 0x1010101010101010
#define PATTERN_3_5 0x2020202020202020
#define PATTERN_3_6 0x4040404040404040
#define PATTERN_3_7 0x8080808080808080
#define PATTERN_4_0 0x0101010101010101
#define PATTERN_4_1 0xfefefefefefefefe
#define PATTERN_4_2 0x0202020202020202
#define PATTERN_4_3 0xfdfdfdfdfdfdfdfd
#define PATTERN_4_4 0x0404040404040404
#define PATTERN_4_5 0xfbfbfbfbfbfbfbfb
#define PATTERN_4_6 0x0808080808080808
#define PATTERN_4_7 0xf7f7f7f7f7f7f7f7
#define PATTERN_5_0 0xfefefefefefefefe
#define PATTERN_5_1 0xfdfdfdfdfdfdfdfd
#define PATTERN_5_2 0xfbfbfbfbfbfbfbfb
#define PATTERN_5_3 0xf7f7f7f7f7f7f7f7
#define PATTERN_5_4 0xefefefefefefefef
#define PATTERN_5_5 0xdfdfdfdfdfdfdfdf
#define PATTERN_5_6 0xbfbfbfbfbfbfbfbf
#define PATTERN_5_7 0x7f7f7f7f7f7f7f7f

#define PATTERN_JUST0   0x0000000000000000
#define PATTERN_JUST1   0xffffffffffffffff

#define PATTERN_JUSTA   0xaaaaaaaaaaaaaaaa
#define PATTERN_JUST5   0x5555555555555555
#define PATTERN_FiveA   0x55555555aaaaaaaa
#define PATTERN_ZEROONE 0x00000000ffffffff
#define PATTERN_L8b10b  0x1616161616161616
#define PATTERN_S8b10b  0xb5b5b5b5b5b5b5b5
#define PATTERN_Five7   0x5555555755575555
#define PATTERN_Zero2fd 0x00020002fffdfffd

#define MAX_ERRORS  0x10
    TTYDBG("msize = ")
    move    a0, msize
    bal     hexserial
    nop
13: //pattern WalkOnes
#if 0
    TTYDBG("\r\nPattern WalkOnes Test...\r\n")
    dli     t8, MAX_ERRORS
    dli     t1, TEST_BASE
    dli     t7, 0x200000
    dsubu   t7, msize, t7   //msize-2M
    daddu   t3, t1, t7
    dli     t2, 0x200    //address interval
    //debug--------
    TTYDBG("Test address range: 0x")
    move    a0, t1
    bal     hexserial
    nop
    TTYDBG("~0x")
    move    a0, t3
    bal     hexserial
    nop
    TTYDBG("  @@  address interval: 0x")
    move    a0, t2
    bal     hexserial
    nop
    TTYDBG("\r\n")
    //---------debug
//write memory
    dli     t1, TEST_BASE
1:
    dli     t7, PATTERN_3_0
    sd      t7, 0x0(t1)
    dli     t7, PATTERN_3_1
    sd      t7, 0x8(t1)
    dli     t7, PATTERN_3_2
    sd      t7, 0x10(t1)
    dli     t7, PATTERN_3_3
    sd      t7, 0x18(t1)
    dli     t7, PATTERN_3_4
    sd      t7, 0x20(t1)
    dli     t7, PATTERN_3_5
    sd      t7, 0x28(t1)
    dli     t7, PATTERN_3_6
    sd      t7, 0x30(t1)
    dli     t7, PATTERN_3_7
    sd      t7, 0x38(t1)

    daddu   t1, t1, t2
    bltu    t1, t3, 1b
    nop
	TTYDBG("write done...\r\n")
//read memory and compare
    dli     t1, TEST_BASE
1:
    ld      t4, 0x0(t1)
    dli     t0, PATTERN_3_0
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    bal     hexserial64_1
    nop
    daddiu  t8, t8, -1
    bltz    t8, 14f  //detect enough errors, go to next test
    nop
2:
    ld      t4, 0x8(t1)
    dli     t0, PATTERN_3_1
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x8 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x8
    daddiu  t8, t8, -1
2:
    ld      t4, 0x10(t1)
    dli     t0, PATTERN_3_2
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x10
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x10
    daddiu  t8, t8, -1
2:
    ld      t4, 0x18(t1)
    dli     t0, PATTERN_3_3
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x18 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x18
    daddiu  t8, t8, -1
2:
    ld      t4, 0x20(t1)
    dli     t0, PATTERN_3_4
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x20
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x20
    daddiu  t8, t8, -1
2:
    ld      t4, 0x28(t1)
    dli     t0, PATTERN_3_5
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x28 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x28
    daddiu  t8, t8, -1
2:
    ld      t4, 0x30(t1)
    dli     t0, PATTERN_3_6
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x30
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x30
    daddiu  t8, t8, -1
2:
    ld      t4, 0x38(t1)
    dli     t0, PATTERN_3_7
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x38 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x38
    daddiu  t8, t8, -1
2:
    bltz    t8, 14f  //detect enough errors, go to next test
    nop
    
    daddu   t1, t1, t2
    //check address range
    bltu    t1, t3, 1b
    nop

    TTYDBG("Pattern Testing done.\r\n")
#endif
14: //pattern WalkInvOnes
#if 0
    TTYDBG("\r\nPattern WalkInvOnes Test...\r\n")
    dli     t8, MAX_ERRORS
    dli     t1, TEST_BASE
    dli     t7, 0x200000
    dsubu   t7, msize, t7   //msize-2M
    daddu   t3, t1, t7
    dli     t2, 0x200    //address interval
    //debug--------
    TTYDBG("Test address range: 0x")
    move    a0, t1
    bal     hexserial
    nop
    TTYDBG("~0x")
    move    a0, t3
    bal     hexserial
    nop
    TTYDBG("  @@  address interval: 0x")
    move    a0, t2
    bal     hexserial
    nop
    TTYDBG("\r\n")
    //---------debug
//write memory
    dli     t1, TEST_BASE
1:
    dli     t7, PATTERN_4_0
    sd      t7, 0x0(t1)
    dli     t7, PATTERN_4_1
    sd      t7, 0x8(t1)
    dli     t7, PATTERN_4_2
    sd      t7, 0x10(t1)
    dli     t7, PATTERN_4_3
    sd      t7, 0x18(t1)
    dli     t7, PATTERN_4_4
    sd      t7, 0x20(t1)
    dli     t7, PATTERN_4_5
    sd      t7, 0x28(t1)
    dli     t7, PATTERN_4_6
    sd      t7, 0x30(t1)
    dli     t7, PATTERN_4_7
    sd      t7, 0x38(t1)

    daddu   t1, t1, t2
    bltu    t1, t3, 1b
    nop
	TTYDBG("write done...\r\n")
//read memory and compare
    dli     t1, TEST_BASE
1:
    ld      t4, 0x0(t1)
    dli     t0, PATTERN_4_0
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    bal     hexserial64_1
    nop
    daddiu  t8, t8, -1
    bltz    t8, 15f  //detect enough errors, go to next test
    nop
2:
    ld      t4, 0x8(t1)
    dli     t0, PATTERN_4_1
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x8 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x8
    daddiu  t8, t8, -1
2:
    ld      t4, 0x10(t1)
    dli     t0, PATTERN_4_2
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x10
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x10
    daddiu  t8, t8, -1
2:
    ld      t4, 0x18(t1)
    dli     t0, PATTERN_4_3
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x18 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x18
    daddiu  t8, t8, -1
2:
    ld      t4, 0x20(t1)
    dli     t0, PATTERN_4_4
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x20
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x20
    daddiu  t8, t8, -1
2:
    ld      t4, 0x28(t1)
    dli     t0, PATTERN_4_5
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x28 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x28
    daddiu  t8, t8, -1
2:
    ld      t4, 0x30(t1)
    dli     t0, PATTERN_4_6
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x30
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x30
    daddiu  t8, t8, -1
2:
    ld      t4, 0x38(t1)
    dli     t0, PATTERN_4_7
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x38 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x38
    daddiu  t8, t8, -1
2:
    bltz    t8, 15f  //detect enough errors, go to next test
    nop
    
    daddu   t1, t1, t2
    //check address range
    bltu    t1, t3, 1b
    nop

    TTYDBG("Pattern Testing done.\r\n")
#endif
15: //pattern WalkZeros
#if 0
    TTYDBG("\r\nPattern WalkZeros Test...\r\n")
    dli     t8, MAX_ERRORS
    dli     t1, TEST_BASE
    dli     t7, 0x200000
    dsubu   t7, msize, t7   //msize-2M
    daddu   t3, t1, t7
    dli     t2, 0x200    //address interval
    //debug--------
    TTYDBG("Test address range: 0x")
    move    a0, t1
    bal     hexserial
    nop
    TTYDBG("~0x")
    move    a0, t3
    bal     hexserial
    nop
    TTYDBG("  @@  address interval: 0x")
    move    a0, t2
    bal     hexserial
    nop
    TTYDBG("\r\n")
    //---------debug
//write memory
    dli     t1, TEST_BASE
1:
    dli     t7, PATTERN_5_0
    sd      t7, 0x0(t1)
    dli     t7, PATTERN_5_1
    sd      t7, 0x8(t1)
    dli     t7, PATTERN_5_2
    sd      t7, 0x10(t1)
    dli     t7, PATTERN_5_3
    sd      t7, 0x18(t1)
    dli     t7, PATTERN_5_4
    sd      t7, 0x20(t1)
    dli     t7, PATTERN_5_5
    sd      t7, 0x28(t1)
    dli     t7, PATTERN_5_6
    sd      t7, 0x30(t1)
    dli     t7, PATTERN_5_7
    sd      t7, 0x38(t1)

    daddu   t1, t1, t2
    bltu    t1, t3, 1b
    nop
	TTYDBG("write done...\r\n")
//read memory and compare
    dli     t1, TEST_BASE
1:
    ld      t4, 0x0(t1)
    dli     t0, PATTERN_5_0
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    bal     hexserial64_1
    nop
    daddiu  t8, t8, -1
    bltz    t8, 21f  //detect enough errors, go to next test
    nop
2:
    ld      t4, 0x8(t1)
    dli     t0, PATTERN_5_1
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x8 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x8
    daddiu  t8, t8, -1
2:
    ld      t4, 0x10(t1)
    dli     t0, PATTERN_5_2
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x10
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x10
    daddiu  t8, t8, -1
2:
    ld      t4, 0x18(t1)
    dli     t0, PATTERN_5_3
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x18 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x18
    daddiu  t8, t8, -1
2:
    ld      t4, 0x20(t1)
    dli     t0, PATTERN_5_4
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x20
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x20
    daddiu  t8, t8, -1
2:
    ld      t4, 0x28(t1)
    dli     t0, PATTERN_5_5
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x28 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x28
    daddiu  t8, t8, -1
2:
    ld      t4, 0x30(t1)
    dli     t0, PATTERN_5_6
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x30
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x30
    daddiu  t8, t8, -1
2:
    ld      t4, 0x38(t1)
    dli     t0, PATTERN_5_7
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x38 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x38
    daddiu  t8, t8, -1
2:
    bltz    t8, 21f  //detect enough errors, go to next test
    nop
    
    daddu   t1, t1, t2
    //check address range
    bltu    t1, t3, 1b
    nop

    TTYDBG("Pattern Testing done.\r\n")
#endif
16: //pattern Diff Burst Test
#if 1
    //initialization
    dli     t9, 0
    dli     t6, PATTERN_BASE
    dli     t2, 0x20    //address interval
    dli     t1, TEST_BASE
    dsrl    t7, msize, 3    //msize/8
    daddu   t3, t1, t7  //set max address t3
/*****************
* loop control
* t9:
* 1~16: Just0,Just1 set
* 17~32%16  Justb5, Just4a
* 33~48%32  JustA, Just5
*******************/
10:
    daddiu  t9, t9, 0x1
    dli     t7, 16
    //bgtu    t9, t7, 1f    //normal code
    bgtu    t9, t7, 3f  //temp code, only test 1~16
    nop
    TTYDBG("\r\nPattern 0-f Test....\r\n")
    dli     t2, 0x200    //address interval
    dli     t1, TEST_BASE
    dli     t7, 0x200000
    dsubu   t7, msize, t7    //msize
    daddu   t3, t1, t7  //set test limit address t3
    dli     t7, 0
    dli     t0, PATTERN_JUST0
    dli     t5, PATTERN_JUST1
    b       2f
    nop
1:  
    dli     t7, 32
    bgtu    t9, t7, 1f
    nop
    TTYDBG("\r\nPattern b5-4a Test....\r\n")
    dli     t2, 0x400    //address interval
    dli     t1, TEST_BASE
    dli     t7, 0x200000
    dsubu   t7, msize, t7    //msize
    daddu   t3, t1, t7  //set test limit address t3
    dli     t7, 16
    dli     t0, PATTERN_1_0
    dli     t5, PATTERN_1_1
    b       2f
    nop
1:  
    TTYDBG("\r\nPattern a-5 Test....\r\n")
    dli     t2, 0x400    //address interval
    dli     t1, TEST_BASE
    dli     t7, 0x200000
    dsubu   t7, msize, t7    //msize
    daddu   t3, t1, t7  //set test limit address t3
    dli     t7, 32
    dli     t0, PATTERN_JUSTA
    dli     t5, PATTERN_JUST5
    b       2f
    nop
2:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 1
    TTYDBG("Pattern 0000 Test....\r\n")
    sd      t0, 0x0(t6)
    sd      t0, 0x8(t6)
    sd      t0, 0x10(t6)
    sd      t0, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 2
    TTYDBG("Pattern 0001 Test....\r\n")
    sd      t0, 0x0(t6)
    sd      t0, 0x8(t6)
    sd      t0, 0x10(t6)
    sd      t5, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 3
    TTYDBG("Pattern 0010 Test....\r\n")
    sd      t0, 0x0(t6)
    sd      t0, 0x8(t6)
    sd      t5, 0x10(t6)
    sd      t0, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 4
    TTYDBG("Pattern 0011 Test....\r\n")
    sd      t0, 0x0(t6)
    sd      t0, 0x8(t6)
    sd      t5, 0x10(t6)
    sd      t5, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 5
    TTYDBG("Pattern 0100 Test....\r\n")
    sd      t0, 0x0(t6)
    sd      t5, 0x8(t6)
    sd      t0, 0x10(t6)
    sd      t0, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 6
    TTYDBG("Pattern 0101 Test....\r\n")
    sd      t0, 0x0(t6)
    sd      t5, 0x8(t6)
    sd      t0, 0x10(t6)
    sd      t5, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 7
    TTYDBG("Pattern 0110 Test....\r\n")
    sd      t0, 0x0(t6)
    sd      t5, 0x8(t6)
    sd      t5, 0x10(t6)
    sd      t0, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 8
    TTYDBG("Pattern 0111 Test....\r\n")
    sd      t0, 0x0(t6)
    sd      t5, 0x8(t6)
    sd      t5, 0x10(t6)
    sd      t5, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 9
    TTYDBG("Pattern 1000 Test....\r\n")
    sd      t5, 0x0(t6)
    sd      t0, 0x8(t6)
    sd      t0, 0x10(t6)
    sd      t0, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 10
    TTYDBG("Pattern 1001 Test....\r\n")
    sd      t5, 0x0(t6)
    sd      t0, 0x8(t6)
    sd      t0, 0x10(t6)
    sd      t5, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 11
    TTYDBG("Pattern 1010 Test....\r\n")
    sd      t5, 0x0(t6)
    sd      t0, 0x8(t6)
    sd      t5, 0x10(t6)
    sd      t0, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 12
    TTYDBG("Pattern 1011 Test....\r\n")
    sd      t5, 0x0(t6)
    sd      t0, 0x8(t6)
    sd      t5, 0x10(t6)
    sd      t5, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 13
    TTYDBG("Pattern 1100 Test....\r\n")
    sd      t5, 0x0(t6)
    sd      t5, 0x8(t6)
    sd      t0, 0x10(t6)
    sd      t0, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 14
    TTYDBG("Pattern 1101 Test....\r\n")
    sd      t5, 0x0(t6)
    sd      t5, 0x8(t6)
    sd      t0, 0x10(t6)
    sd      t5, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 15
    TTYDBG("Pattern 1110 Test....\r\n")
    sd      t5, 0x0(t6)
    sd      t5, 0x8(t6)
    sd      t5, 0x10(t6)
    sd      t0, 0x18(t6)
    b       2f
    nop
1:
    daddiu  t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9%16 == 16
    TTYDBG("Pattern 1111 Test....\r\n")
    sd      t5, 0x0(t6)
    sd      t5, 0x8(t6)
    sd      t5, 0x10(t6)
    sd      t5, 0x18(t6)
    b       2f
    nop
1:
    // t9 > 48 (all the burst inverse Pattern test done)
    dli     t7, 48
    bgtu    t9, t7, 3f  //go to the end of this loop
    nop
2:
    dli     t8, MAX_ERRORS
    dli     t1, TEST_BASE
    //debug--------
    TTYDBG("Test address range: 0x")
    move    a0, t1
    bal     hexserial
    nop
    TTYDBG("~0x")
    move    a0, t3
    bal     hexserial
    nop
    TTYDBG("  @@  address interval: 0x")
    move    a0, t2
    bal     hexserial
    nop
    TTYDBG("\r\n")
    //---------debug
//write memory
    dli     t1, TEST_BASE
    ld      t0, 0x0(t6)
    ld      t4, 0x8(t6)
    ld      t5, 0x10(t6)
    ld      t7, 0x18(t6)
1:
    sd      t0, 0x0(t1)
    sd      t4, 0x8(t1)
    sd      t5, 0x10(t1)
    sd      t7, 0x18(t1)
    daddu   t1, t1, t2
    bltu    t1, t3, 1b
    nop
	TTYDBG("write done. begin to read and compare...\r\n")
//read memory and compare
    dli     t1, TEST_BASE
1:
    ld      t0, 0x0(t6)
    ld      t4, 0x0(t1)
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    bal     hexserial64_1
    nop
    daddiu  t8, t8, -0x1
    bltz    t8, 10b  //detect enough errors, go to next test
    nop
2:
    ld      t0, 0x8(t6)
    ld      t4, 0x8(t1)
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x8 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x8
    daddiu  t8, t8, -0x1
    bltz    t8, 10b  //detect enough errors, go to next test
    nop
2:
    ld      t0, 0x10(t6)
    ld      t4, 0x10(t1)
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x10 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x10
    daddiu  t8, t8, -0x1
    bltz    t8, 10b  //detect enough errors, go to next test
    nop
2:
    ld      t0, 0x18(t6)
    ld      t4, 0x18(t1)
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x18 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x18
    daddiu  t8, t8, -0x1
    bltz    t8, 10b  //detect enough errors, go to next test
    nop
2:
    daddu   t1, t1, t2
    //check address range
    bltu    t1, t3, 1b
    nop
    TTYDBG("Pattern Testing done.\r\n")
    b       10b
    nop
3:
#endif
//pattern FiveA8
#if 0
    TTYDBG("\r\nPattern FiveA8 Test...\r\n")
    dli     t8, MAX_ERRORS
    dli     t1, TEST_BASE
    dli     t7, 0x200000
    dsubu   t7, msize, t7   //msize-256M
    daddu   t3, t1, t7
    dli     t2, 0x100    //address interval
    //debug--------
    TTYDBG("Test address range: 0x")
    move    a0, t1
    bal     hexserial
    nop
    TTYDBG("~0x")
    move    a0, t3
    bal     hexserial
    nop
    TTYDBG("  @@  address interval: 0x")
    move    a0, t2
    bal     hexserial
    nop
    TTYDBG("\r\n")
    //---------debug
//write memory
    dli     t1, TEST_BASE
1:
    dli     t7, PATTERN_2_0
    sd      t7, 0x0(t1)
    dli     t7, PATTERN_2_1
    sd      t7, 0x8(t1)
    daddu   t1, t1, t2
    bltu    t1, t3, 1b
    nop
	TTYDBG("write done...\r\n")
//read memory and compare
    dli     t1, TEST_BASE
1:
    ld      t4, 0x0(t1)
    dli     t0, PATTERN_2_0
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    bal     hexserial64_1
    nop
    daddiu  t8, t8, -1
    bltz    t8, 16f  //detect enough errors, go to end
    nop
2:
    ld      t4, 0x8(t1)
    dli     t0, PATTERN_2_1
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x8 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -8
    daddiu  t8, t8, -1
2:
    daddu   t1, t1, t2
    //check address range
    bltu    t1, t3, 1b
    nop
    TTYDBG("Pattern Testing done.\r\n")
#endif
16: //pattern JustX Test
#if 0
    //initialization
    dli     t9, 0
    dli     t2, 0x10    //address interval
    dli     t1, TEST_BASE
    dsrl    t7, msize, 3    //msize/8
    daddu   t3, t1, t7  //set max address t3
10:
    //loop control
    daddiu  t9, t9, 0x1
    dli     t7, 1
    bgtu    t9, t7, 1f
    nop
    //t9 == 1
    TTYDBG("\r\nPattern JustA Test...\r\n")
    dli     t0, PATTERN_JUSTA
    b       2f
    nop
1:
    dli     t7, 2
    bgtu    t9, t7, 1f
    nop
    //t9 == 2
    TTYDBG("Pattern Just5 Test...\r\n")
    dli     t0, PATTERN_JUST5
    b       2f
    nop
1:
    dli     t7, 3
    bgtu    t9, t7, 1f
    nop
    //t9 == 3
    TTYDBG("Pattern JustFiveA Test...\r\n")
    dli     t0, PATTERN_FiveA
    b       2f
    nop
1:
    dli     t7, 4
    bgtu    t9, t7, 1f
    nop
    //t9 == 4
    TTYDBG("Pattern JustZeroOne Test...\r\n")
    dli     t0, PATTERN_ZEROONE
    b       2f
    nop
1:
    dli     t7, 5
    bgtu    t9, t7, 1f
    nop
    //t9 == 5
    TTYDBG("Pattern JustL8b10b-16 Test...\r\n")
    dli     t0, PATTERN_L8b10b
    b       2f
    nop
1:
    dli     t7, 6
    bgtu    t9, t7, 1f
    nop
    //t9 == 6
    TTYDBG("Pattern JustS8b10b-b5 Test...\r\n")
    dli     t0, PATTERN_S8b10b
    b       2f
    nop
1:
    dli     t7, 7
    bgtu    t9, t7, 1f
    nop
    //t9 == 7
    TTYDBG("Pattern JustFive7 Test...\r\n")
    dli     t0, PATTERN_Five7
    b       2f
    nop
1:
    dli     t7, 8
    bgtu    t9, t7, 1f
    nop
    //t9 == 8
    TTYDBG("Pattern JustZero2fd Test...\r\n")
    dli     t0, PATTERN_Zero2fd
    b       2f
    nop
1:  
    // t9 > 8 (all the JustX Pattern test done)
    b       3f  //go to the end of this loop
    nop
2:
    dli     t8, MAX_ERRORS
    dli     t1, TEST_BASE
    //debug--------
    TTYDBG("Test address range: 0x")
    move    a0, t1
    bal     hexserial
    nop
    TTYDBG("~0x")
    move    a0, t3
    bal     hexserial
    nop
    TTYDBG("  @@  address interval: 0x")
    move    a0, t2
    bal     hexserial
    nop
    TTYDBG("\r\n")
    //---------debug
//write memory
    dli     t1, TEST_BASE
1:
    sd      t0, 0x0(t1)
    sd      t0, 0x8(t1)
    daddu   t1, t1, t2
    bltu    t1, t3, 1b
    nop
	TTYDBG("write done. begin to read and compare...\r\n")
//read memory and compare
    dli     t1, TEST_BASE
1:
    ld      t4, 0x0(t1)
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    bal     hexserial64_1
    nop
    daddiu  t8, t8, -0x1
    bltz    t8, 10b  //detect enough errors, go to next test
    nop
2:
    ld      t4, 0x8(t1)
    beq     t4, t0, 2f
    nop
    //error detected!!! print address,expected data,read data and reread data
    daddiu  t1, t1, 0x8 //the hexserial64_1 will use t1 directly
    bal     hexserial64_1
    nop
    daddiu  t1, t1, -0x8
    daddiu  t8, t8, -0x1
    bltz    t8, 10b  //detect enough errors, go to next test
    nop
2:
    daddu   t1, t1, t2
    //check address range
    bltu    t1, t3, 1b
    nop
    TTYDBG("Pattern Testing done.\r\n")
    b       10b
    nop
3:
#endif
21: //pattern 11

#if 0   //the code below should be contained in start.S
LEAF(hexserial64_1) //added by cxk
/**********************
!!specially written for DEBUG_MEM 
input:  t1: read address(read only)
        t0: expected data(read only)
        t4: read data
use reg:t5, t7
***********************/
    move    t7,ra
	TTYDBG("\r\naddr 0x")
	dsrl	a0, t1, 32
	bal	    hexserial
	nop
	move	a0, t1
	bal	    hexserial
	nop
    TTYDBG(" expected: ")
	dsrl	a0, t0, 32
	bal	    hexserial
	nop
	move	a0, t0
	bal	    hexserial
	nop
    TTYDBG(" read: ")
	dsrl	a0, t4, 32
	bal	    hexserial
	nop
	move	a0, t4
	bal	    hexserial
	nop
    /* reread the wrong byte, use uncached address*/
    TTYDBG(" reread: ")
    dli     t5, 0xf7ffffffffffffff
    and     t5, t1, t5
    ld      t5, 0(t5)
    nop
	dsrl	a0, t5, 32
	bal	    hexserial
	nop
	move	a0, t5
	bal	    hexserial
	nop
    /* if the reread value differs the first read, print mark */
    beq     t4, t5, 2f
    nop
    TTYDBG("  DDD")
2:
    TTYDBG("\r\n")
    jr    t7    
    nop
END(hexserial64_1)
#endif
